Getting Gigascale Chips

Interconnect IP for Gigascale System-on-Chip

* Tampere University of Technology, Institute of Digital and Computer Systems, P.O.Box 553, FIN-33101 Tampere, Finland. E-mail: [email protected], Tel: +358-3-3654335, Fax +358-3-3653095. ** University of Turku, Laboratory of Electronics and Information Technology, Lemminkäisenkatu 14-18 C, FIN-20014 Turku University, Finland. E-mail: [email protected], Tel: +358-2-3336939, Fax +358-...

Exploring Microprocessor Architectures for Gigascale Integration

As VLSI advances towards billions of fast transistors on a chip (Gigascale Integration, or GSI), it is becoming clear that interconnect issues will dominate. Conventional uniprocessor architectures, developed in an era when interconnect was largely ignored, may be incompatible with this technology. This paper presents a quantitative exploration of architectural alternatives for gigascale techno...

Atlas: a Dynamically Parallelizing Chip-multiprocessor for Gigascale Integration

Single-chip multiprocessors are an important research direction for future microprocessors. The stigma of this approach is that many important applications cannot be automatically parallelized. This chapter presents a single-chip multiprocessor that engages aggressive speculation techniques to enable dynamic parallelization of irregular, sequential binaries. Thread speculation (multiscalar exec...

Throughput-Centric Wave-Pipelined Interconnect Circuits for Gigascale Integration

On Nanoscale Integration and Gigascale Complexity in the Post.Com World

While process technologists are obsessed to follow Moore’s curve down to nanoscale dimensions, design technologists are confronted with gigascale complexity. On the other hand, post-PC and post dotcom products require zero cost, zero energy yet software programmable novel system architectures to be sold in huge volumes and to be designed in exponentially decreasing time. How do we cope with the...